1. Technical Field
The present disclosure relates to a gate driving circuit and a display device having the same. More particularly, the present disclosure relates to a gate driving circuit for driving a number of gate lines using a plurality of shift registers each having a plurality of stages, and an display device having the gate driving circuit.
2. Discussion of the Related Art
A liquid crystal display (LCD) is a device in which an electric field is applied to a liquid crystal substance with an anisotropic dielectric constant, which has been injected between two substrates, and the intensity of the electric field is adjusted to control an amount of light transmitted onto the substrate such that a desired image can be displayed thereon.
A plurality of gate lines parallel to one another and a plurality of data lines crossing the gate lines are formed on the substrate of such an LCD in a state where the gate and data lines are insulated from each other, and each pixel is defined in a region surrounded by these gate and data lines. A thin film transistor (hereinafter, referred to as “TFT”) and a pixel electrode are formed at a portion where the respective gate and data lines cross each other.
The LCD includes a gate driving circuit for driving the gate lines and a source driving circuit for driving the data lines. If the gate driving circuit applies a predetermined voltage to the gate line, the data line and the pixel electrode connected respectively to both ends of the TFT are electrically connected with each other. At this time, the source driving circuit applies a predetermined data voltage to the pixel electrode through the data line such that the LCD can be driven.
The gate driving circuit can be driven using a shift register.
FIG. 1 is a block diagram illustrating a shift register constituting a gate driving circuit of an LCD panel according to the prior art.
The shift register comprises a plurality of stages 21, each of which includes a first output terminal GOUT for driving each of the gate lines G1 to G5, a second output terminal SOUT, an input terminal IN, a control terminal CT, a clock input terminal CK, a ground voltage terminal VSS, and a driving voltage terminal VDD.
The stage 21 is connected to each of the gate lines and the second output terminal SOUT is connected both to the input terminal IN of the next stage and the control terminal CT of the previous stage such that the stages are dependently connected to one another to thereby drive all the gate lines.
In order to smoothly display a moving image on the LCD, the gate line should be driven at least 60 times per second. However, since the shift register so configured has a low operating speed, it is difficult to drive up to 400 gate lines as typically required.